As the data processing speed of computer systems increases, the need for faster memory speeds also increases. Conventional (or single port) DRAMs, due to their high density and relatively low manufacturing cost, are presently used for the majority of memory applications. Conventional DRAMs, however, are not feasible for many growing memory applications. While cost effective, conventional DRAMs have a lower operating speed relative to other memory types.
Faster memory types include static random access memories (SRAMs) and dual-port DRAMs (called video RAMs, or VRAMs, in some instances). SRAMs have higher operating speeds, but have cells of a more complex design and larger size. Dual-port DRAMs provide speed advantages over conventional DRAMs by providing an additional input/output port to the memory array. In conventional DRAMs, read and write operations may never occur simultaneously, as both operations occur through a single random access port. In contrast, in a dual-port DRAM, the second port (most often a serial port) is provided in addition to the random access port. Data is read and written by transferring an entire array row at one time between a serial shift register and the array. The serial shift register receives and outputs the data in a serial manner.
U.S. Pat. No. 4,281,401 issued to Redwine et al., describes a semiconductor memory of open bit line architecture having a serial input/output design. The memory device includes an array having a serial shift register connected thereto. While providing a serial input and output, the invention of Redwine et al. is a one port design, providing access to the array on a row-by-row basis only.
U.S. Pat. No. 4,541,075 issued to Dill et al., describes a semiconductor memory having two input/output ports. The first port is a s random access port which allows a single bit to be read from, or written to the array. The second port is a row buffer serial register for allowing the reading or writing of an entire row. In a write operation for the second port, data are entered into the serial register in a serial fashion and written to a row in a single parallel write operation. In a read operation, an entire row is written in a parallel operation to the row buffer serial register, and the data is output in a serial fashion. The column decoders, sense amplifiers, and row buffer serial register are all disposed on one side of the array.
U.S. Pat. No. 4,769,789 issued to Noguchi et al., describes a semiconductor memory having an array that includes both random access and serial access to the memory cells within. In an open bit line embodiment of the invention, a row of sense amplifiers is centrally disposed within the array, a column decoder is disposed on one side of the array, while on the other side of the array are a first row a transfer gates, a row of latches, a row of serial gates, and a row of shift registers. In a random operation the column decoder activates gates surrounding the sense amplifier of a selected column. In serial operation the column decoder provides the first register from which serial data transfer is to begin. In a "folded" bit line embodiment of the '789 patent, a row of sense amplifiers, a row of gates and a column decoder are disposed on one side of the array while a row of transfer gates, latches, serial gates and a shift register are disposed on the opposite side of the array. One embodiment of Noguchi et al. increases the memory size using two identical arrays together.
In the prior art it is known to provide a dual-port DRAM composed of multiple arrays, each having a random access port and a serial access port. Referring now to FIG. 1, a dual-port DRAM of the prior art is shown having this configuration. The dual-port DRAM 1 has four arrays, labeled 2a-2d. Each array has an accompanying column decoder section 3a-3d, row decoder section 4a-4d, a row of sense amplifiers 5a-5d, and a serial output portion 6a-6d. Column decoders 3a and 3b, and the row of sense amplifiers 5a and 5b occupy the space between arrays 2a and 2b. Similarly, column decoders 3c and 3d and sense amplifier rows 5c and 5d are situated between arrays 2c and 2d.
A serial input/output section 6 is provided for each array 2. The serial input/output sections 6b-6c are situated between arrays 2b and 2c opposite from their respective column decoders (3b and 3c) and sense amplifier rows (5b and 5c). Serial output sections 6a and 6d are on the ends of the arrays. Each serial input/output section 6a-6d includes a latching serial shift register arrangement, as is well known in the art. The example set forth in FIG. 1 illustrates a "by four" (.times.4) dual-port DRAM arrangement. Random read or write operations to one bit on each array can occur simultaneously. At the same time, each array can provide a row read or write to its respective serial output portion 6a-6d. The serial output portions 6a-6d provide four serial output ports.
While a number of dual-port DRAM designs exist in the prior art, the designs are complex requiring a large amount of silicon space for the various device sections. Process improvements can provide smaller device geometries, but such improvement have limitations. Thus, it is always desirable to provide alternative designs that reduce the physical area of a memory device.